As semiconductor device circuit line dimensions are reduced below 0.5 micron (".mu.m"), a multi-layer metallization process faces several challenges, including adequate metal step coverage for electrical interconnects, clean patterning on individual layers and planarization. Metal deposition to define an electrical contact or an electrical interconnect between two layers is often performed by metal sputtering. Where an electrical via for interconnect purposes has a high aspect ratio, or ratio of depth to diameter of the via, traditional metal sputtering, such as TiW/Al/TiW, has become a limiting process in submicron designs, because of poor metal step coverage, poor electro-migration resistance and higher-than-acceptable electrical contact resistance.
An attractive alternative here is chemical vapor deposition ("CVD") of tungsten in the vias and on electrical contact regions. However, this requires: (1) deposition with high selectively on silicon, on silicides and on metals and not on adjacent insulator oxides; (2) excellent resistance to electro-migration; and (3) improved conformal step coverage on vias with aspect ratios &gt;1.
At least four problems must be overcome using this approach. First, trapping of a polycrystalline insulator material, such as titanium trifluoride, TiF.sub.3, at the W/TiS.sub.2 interface adjacent to a via or an electrical contact will induce high contact resistance. Second, presence of even a small amount of oxygen, such as titanium oxide, at the top or exposed layer of titanium silicide, TiSi.sub.2, depresses nucleation of tungsten deposited by CVD on TiSi.sub.2. Third, if tungsten is to be used to form an electrical contact or to provide an electrical interconnect by filling a via, the area of the contact and the depth and diameter of the via can vary greatly. For example, a deep and wide via might be filled only partially and a shallow via might quickly overfill, for different depth vias on a single layer of a multi-layer semiconductor circuit. Fourth, selectivity loss on an oxide surface in tungsten deposition may induce severe defects and jeopardize circuit yield. During CVD of tungsten, an exposed adjacent oxide surface may become contaminated or altered by a photoresist patterning process so that the altered oxide behaves as a tungsten nucleation layer that will induce severe defects, cause short circuits and jeopardize circuit yield.
What is needed is a tungsten deposition process for electrical contacts and vias that (1) is highly selective for W deposition on silicon, silicide and metal, (2) allows W deposition in vias and as electrical contacts over a wide range of via depths and diameters and contact areas, and (3) provides very low contact resistance at a W/TiSi.sub.x interface.